[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0-rc1 spec

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:127
   assert((RVVVectorBitsMin == 0 ||
-          (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 &&
+          (RVVVectorBitsMin >= 32 && RVVVectorBitsMax <= 65536 &&
            isPowerOf2_32(RVVVectorBitsMin))) &&
----------------
craig.topper wrote:
> Some of the callers of this will break if it returns a value less than 64. We need to limit ELEN to 32 if VLEN is 32. And we can't use LMUL=1/8 with i8 vectors, or LMUL=1/4 with i16 vector, or LMUL=1/2 with i32 vector.
We have an implicit assumption that VLEN >= 64 from our VLA types. I suggest use 64 as the lower bound and add a FIXME here for VLEN is 32.


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Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:134
          "maximum!");
+  assert(RVVVectorBitsMin >= ZvlLen &&
+         "Minimum V extension vector length should be at least the length "
----------------
Should it be `RVVVectorBitsMin < ZvlLen`?

I suggest to return 0 and print a warning message for users.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694