[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0-rc1 spec

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

Those rule are unclear to me too, I created an issue on vector spec, I guess we need writing few special rule for those extensions...

https://github.com/riscv/riscv-v-spec/issues/723

In D108694#2966553 <https://reviews.llvm.org/D108694#2966553>, @craig.topper wrote:

> I think we need to visit some larger aspects of our vector implementation. Here are some thoughts.
>
> -Most uses of Subtarget.hasStdExtV() don't really mean what the spec calls the standard V extension. They just means that we have vector instructions. Could be V, could be one of the Zve32* or Zve64* extensions.
> -V extension passed to -march should imply at least Zvl128b.
> -V extension passed to -march should enable F and D.
> -Does Zvl32b passed to march enable vector instructions? Or do we still need Zve32* or Zve64* or V?
> -If Zvl32b is in effect the i64 and f64 RVV intrinsics need to be disabled.




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