[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0-rc1 spec

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:112
     return 0;
-  assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
+  assert(RVVVectorBitsMax >= 32 && RVVVectorBitsMax <= 65536 &&
          isPowerOf2_32(RVVVectorBitsMax) &&
----------------
craig.topper wrote:
> The max should be greater than ZvlLen right?
Should it be less than or equal to ZvlLen? I would suggest to return 0 when `RVVVectorBitsMax > ZvlLen`.
The value also needs to `>= 64`.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108694/new/

https://reviews.llvm.org/D108694