[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0-rc1 spec

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I think we need to visit some larger aspects of our vector implementation. Here are some thoughts.

-Most uses of Subtarget.hasStdExtV() don't really mean what the spec calls the standard V extension. They just means that we have vector instructions. Could be V, could be one of the Zve32* or Zve64* extensions.
-V extension passed to -march should imply at least Zvl128b.
-V extension passed to -march should enable F and D.
-Does Zvl32b passed to march enable vector instructions? Or do we still need Zve32* or Zve64* or V?
-If Zvl32b is in effect the i64 and f64 RVV intrinsics need to be disabled.


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https://reviews.llvm.org/D108694