[PATCH] D108701: [X86][SchedModel] Fix latency of the Hi register write of MULX (PR51495).

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri accepted this revision.
lebedev.ri added a comment.
This revision is now accepted and ready to land.

LGTM!
@RKSimon ?



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Comment at: llvm/lib/Target/X86/X86ScheduleZnver3.td:13
 //  * AMD Software Optimization Guide for AMD Family 19h Processors.
-//    https://www.amd.com/system/files/TechDocs/56665.zip
+///    https://www.amd.com/system/files/TechDocs/56665.zip
 //  * The microarchitecture of Intel, AMD and VIA CPUs, By Agner Fog
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drop this


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