[PATCH] D108701: [X86][SchedModel] Fix latency of the Hi register write of MULX (PR51495).

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ScheduleZnver3.td:13
 //  * AMD Software Optimization Guide for AMD Family 19h Processors.
-//    https://www.amd.com/system/files/TechDocs/56665.zip
+///    https://www.amd.com/system/files/TechDocs/56665.zip
 //  * The microarchitecture of Intel, AMD and VIA CPUs, By Agner Fog
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lebedev.ri wrote:
> drop this
Whoops.
No idea how I ended up modifying that line...
Nice catch!


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https://reviews.llvm.org/D108701