[PATCH] D108701: [X86][SchedModel] Fix latency of the Hi register write of MULX (PR51495).

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, spatel, craig.topper, lebedev.ri.
Herald added subscribers: pengfei, gbedwell, hiraditya.
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Before this patch, WriteIMulH reported a latency value which is correct for 
the RR variant of MULX, but not for the RM variant.

This patch fixes the issue by introducing a new WriteIMulHLd, which is meant
to be used only by the RM variant of MULX.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108701

Files:
  llvm/lib/Target/X86/X86InstrArithmetic.td
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/lib/Target/X86/X86Schedule.td
  llvm/lib/Target/X86/X86ScheduleAtom.td
  llvm/lib/Target/X86/X86ScheduleBdVer2.td
  llvm/lib/Target/X86/X86ScheduleBtVer2.td
  llvm/lib/Target/X86/X86ScheduleSLM.td
  llvm/lib/Target/X86/X86ScheduleZnver1.td
  llvm/lib/Target/X86/X86ScheduleZnver2.td
  llvm/lib/Target/X86/X86ScheduleZnver3.td
  llvm/test/tools/llvm-mca/X86/Haswell/mulx-hi-read-advance.s
  llvm/test/tools/llvm-mca/X86/SkylakeClient/mulx-hi-read-advance.s
  llvm/test/tools/llvm-mca/X86/Znver2/mulx-hi-read-advance.s
  llvm/test/tools/llvm-mca/X86/Znver3/mulx-hi-read-advance.s

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