[PATCH] D108276: [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


================
Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:7412
+  if (SrcTy.isScalar()) {
+    assert(DstTy.isScalar() && "Unexpected dst type");
+    if (DstTy.getSizeInBits() > SrcTy.getSizeInBits())
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I think this assert should be something in the verifier?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108276/new/

https://reviews.llvm.org/D108276