[PATCH] D108276: [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, arsenm, jroelofs.
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Herald added subscribers: hiraditya, kristof.beyls, rovka.
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Herald added a subscriber: wdng.

For some reductions like G_VECREDUCE_OR on AArch64, we need to scalarize
completely if the source is <= 64b. This change adds support for that in
the legalizer. If the source has a pow-2 num elements, then we can do
a tree reduction using the scalar operation in the individual elements.
Otherwise, we just create a sequential chain of operations.

For AArch64, we only need to scalarize if the input is <64b. If it's great than
64b then we can first do a fewElements step to 64b, taking advantage of vector
instructions until we reach the point of scalarization.

I also had to relax the verifier checks for reductions because the intrinsics
support <1 x EltTy> types, which we lower to scalars for GlobalISel.

There are still some codegen deficiencies in the generated code, but those can
be addressed later.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108276

Files:
  llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  llvm/test/CodeGen/AArch64/reduce-or.ll
  llvm/test/MachineVerifier/test_vector_reductions.mir

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