[llvm] 45e1a6b - [AArch64][GlobalISel] Legalize scalar G_FMINNUM + G_FMAXNUM
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 18 13:30:19 PDT 2021
Author: Jessica Paquette
Date: 2021-08-18T13:30:03-07:00
New Revision: 45e1a6bd2589469be526c2213598b9847a655fcb
URL: https://github.com/llvm/llvm-project/commit/45e1a6bd2589469be526c2213598b9847a655fcb
DIFF: https://github.com/llvm/llvm-project/commit/45e1a6bd2589469be526c2213598b9847a655fcb.diff
LOG: [AArch64][GlobalISel] Legalize scalar G_FMINNUM + G_FMAXNUM
For subtargets with full FP16, this is legal for s16, s32, and s64. Without
full FP16, it's legal for s32 and s64.
For s128, this is a libcall.
We also support some vector types, but for now, let's just support scalars.
Differential Revision: https://reviews.llvm.org/D108259
Added:
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index b28eef9d2223..bbc3df391da8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -729,6 +729,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_ISNAN).lower();
+ // TODO: Vector types.
+ getActionDefinitionsBuilder({G_FMAXNUM, G_FMINNUM})
+ .legalFor({MinFPScalar, s32, s64})
+ .libcallFor({s128})
+ .minScalar(0, MinFPScalar);
+
getLegacyLegalizerInfo().computeTables();
verify(*ST.getInstrInfo());
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
new file mode 100644
index 000000000000..e1dabeb5e9b4
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
@@ -0,0 +1,115 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=FP16
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=NO-FP16
+...
+---
+name: s16_legal_with_full_fp16
+alignment: 4
+body: |
+ bb.0:
+ liveins: $h0, $h1
+ ; FP16-LABEL: name: s16_legal_with_full_fp16
+ ; FP16: %a:_(s16) = COPY $h0
+ ; FP16: %b:_(s16) = COPY $h1
+ ; FP16: %maxnum:_(s16) = G_FMAXNUM %a, %b
+ ; FP16: $h0 = COPY %maxnum(s16)
+ ; FP16: RET_ReallyLR implicit $h0
+ ; NO-FP16-LABEL: name: s16_legal_with_full_fp16
+ ; NO-FP16: %a:_(s16) = COPY $h0
+ ; NO-FP16: %b:_(s16) = COPY $h1
+ ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %a(s16)
+ ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %b(s16)
+ ; NO-FP16: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[FPEXT]], [[FPEXT1]]
+ ; NO-FP16: %maxnum:_(s16) = G_FPTRUNC [[FMAXNUM]](s32)
+ ; NO-FP16: $h0 = COPY %maxnum(s16)
+ ; NO-FP16: RET_ReallyLR implicit $h0
+ %a:_(s16) = COPY $h0
+ %b:_(s16) = COPY $h1
+ %maxnum:_(s16) = G_FMAXNUM %a, %b
+ $h0 = COPY %maxnum(s16)
+ RET_ReallyLR implicit $h0
+
+...
+---
+name: s32_legal
+alignment: 4
+body: |
+ bb.0:
+ liveins: $s0, $s1
+ ; FP16-LABEL: name: s32_legal
+ ; FP16: %a:_(s32) = COPY $s0
+ ; FP16: %b:_(s32) = COPY $s1
+ ; FP16: %maxnum:_(s32) = G_FMAXNUM %a, %b
+ ; FP16: $s0 = COPY %maxnum(s32)
+ ; FP16: RET_ReallyLR implicit $s0
+ ; NO-FP16-LABEL: name: s32_legal
+ ; NO-FP16: %a:_(s32) = COPY $s0
+ ; NO-FP16: %b:_(s32) = COPY $s1
+ ; NO-FP16: %maxnum:_(s32) = G_FMAXNUM %a, %b
+ ; NO-FP16: $s0 = COPY %maxnum(s32)
+ ; NO-FP16: RET_ReallyLR implicit $s0
+ %a:_(s32) = COPY $s0
+ %b:_(s32) = COPY $s1
+ %maxnum:_(s32) = G_FMAXNUM %a, %b
+ $s0 = COPY %maxnum(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: s64_legal
+alignment: 4
+body: |
+ bb.0:
+ liveins: $d0, $d1
+ ; FP16-LABEL: name: s64_legal
+ ; FP16: %a:_(s64) = COPY $d0
+ ; FP16: %b:_(s64) = COPY $d1
+ ; FP16: %maxnum:_(s64) = G_FMAXNUM %a, %b
+ ; FP16: $d0 = COPY %maxnum(s64)
+ ; FP16: RET_ReallyLR implicit $d0
+ ; NO-FP16-LABEL: name: s64_legal
+ ; NO-FP16: %a:_(s64) = COPY $d0
+ ; NO-FP16: %b:_(s64) = COPY $d1
+ ; NO-FP16: %maxnum:_(s64) = G_FMAXNUM %a, %b
+ ; NO-FP16: $d0 = COPY %maxnum(s64)
+ ; NO-FP16: RET_ReallyLR implicit $d0
+ %a:_(s64) = COPY $d0
+ %b:_(s64) = COPY $d1
+ %maxnum:_(s64) = G_FMAXNUM %a, %b
+ $d0 = COPY %maxnum(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: s128_libcall
+alignment: 4
+body: |
+ bb.0:
+ liveins: $q0, $q1
+ ; FP16-LABEL: name: s128_libcall
+ ; FP16: %a:_(s128) = COPY $q0
+ ; FP16: %b:_(s128) = COPY $q1
+ ; FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; FP16: $q0 = COPY %a(s128)
+ ; FP16: $q1 = COPY %b(s128)
+ ; FP16: BL &fmaxl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
+ ; FP16: %maxnum:_(s128) = COPY $q0
+ ; FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; FP16: $q0 = COPY %maxnum(s128)
+ ; FP16: RET_ReallyLR implicit $q0
+ ; NO-FP16-LABEL: name: s128_libcall
+ ; NO-FP16: %a:_(s128) = COPY $q0
+ ; NO-FP16: %b:_(s128) = COPY $q1
+ ; NO-FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; NO-FP16: $q0 = COPY %a(s128)
+ ; NO-FP16: $q1 = COPY %b(s128)
+ ; NO-FP16: BL &fmaxl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
+ ; NO-FP16: %maxnum:_(s128) = COPY $q0
+ ; NO-FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; NO-FP16: $q0 = COPY %maxnum(s128)
+ ; NO-FP16: RET_ReallyLR implicit $q0
+ %a:_(s128) = COPY $q0
+ %b:_(s128) = COPY $q1
+ %maxnum:_(s128) = G_FMAXNUM %a, %b
+ $q0 = COPY %maxnum(s128)
+ RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
new file mode 100644
index 000000000000..cb6f287b857b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
@@ -0,0 +1,115 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=FP16
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=NO-FP16
+...
+---
+name: s16_legal_with_full_fp16
+alignment: 4
+body: |
+ bb.0:
+ liveins: $h0, $h1
+ ; FP16-LABEL: name: s16_legal_with_full_fp16
+ ; FP16: %a:_(s16) = COPY $h0
+ ; FP16: %b:_(s16) = COPY $h1
+ ; FP16: %minnum:_(s16) = G_FMINNUM %a, %b
+ ; FP16: $h0 = COPY %minnum(s16)
+ ; FP16: RET_ReallyLR implicit $h0
+ ; NO-FP16-LABEL: name: s16_legal_with_full_fp16
+ ; NO-FP16: %a:_(s16) = COPY $h0
+ ; NO-FP16: %b:_(s16) = COPY $h1
+ ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %a(s16)
+ ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %b(s16)
+ ; NO-FP16: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[FPEXT]], [[FPEXT1]]
+ ; NO-FP16: %minnum:_(s16) = G_FPTRUNC [[FMINNUM]](s32)
+ ; NO-FP16: $h0 = COPY %minnum(s16)
+ ; NO-FP16: RET_ReallyLR implicit $h0
+ %a:_(s16) = COPY $h0
+ %b:_(s16) = COPY $h1
+ %minnum:_(s16) = G_FMINNUM %a, %b
+ $h0 = COPY %minnum(s16)
+ RET_ReallyLR implicit $h0
+
+...
+---
+name: s32_legal
+alignment: 4
+body: |
+ bb.0:
+ liveins: $s0, $s1
+ ; FP16-LABEL: name: s32_legal
+ ; FP16: %a:_(s32) = COPY $s0
+ ; FP16: %b:_(s32) = COPY $s1
+ ; FP16: %minnum:_(s32) = G_FMINNUM %a, %b
+ ; FP16: $s0 = COPY %minnum(s32)
+ ; FP16: RET_ReallyLR implicit $s0
+ ; NO-FP16-LABEL: name: s32_legal
+ ; NO-FP16: %a:_(s32) = COPY $s0
+ ; NO-FP16: %b:_(s32) = COPY $s1
+ ; NO-FP16: %minnum:_(s32) = G_FMINNUM %a, %b
+ ; NO-FP16: $s0 = COPY %minnum(s32)
+ ; NO-FP16: RET_ReallyLR implicit $s0
+ %a:_(s32) = COPY $s0
+ %b:_(s32) = COPY $s1
+ %minnum:_(s32) = G_FMINNUM %a, %b
+ $s0 = COPY %minnum(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: s64_legal
+alignment: 4
+body: |
+ bb.0:
+ liveins: $d0, $d1
+ ; FP16-LABEL: name: s64_legal
+ ; FP16: %a:_(s64) = COPY $d0
+ ; FP16: %b:_(s64) = COPY $d1
+ ; FP16: %minnum:_(s64) = G_FMINNUM %a, %b
+ ; FP16: $d0 = COPY %minnum(s64)
+ ; FP16: RET_ReallyLR implicit $d0
+ ; NO-FP16-LABEL: name: s64_legal
+ ; NO-FP16: %a:_(s64) = COPY $d0
+ ; NO-FP16: %b:_(s64) = COPY $d1
+ ; NO-FP16: %minnum:_(s64) = G_FMINNUM %a, %b
+ ; NO-FP16: $d0 = COPY %minnum(s64)
+ ; NO-FP16: RET_ReallyLR implicit $d0
+ %a:_(s64) = COPY $d0
+ %b:_(s64) = COPY $d1
+ %minnum:_(s64) = G_FMINNUM %a, %b
+ $d0 = COPY %minnum(s64)
+ RET_ReallyLR implicit $d0
+
+...
+---
+name: s128_libcall
+alignment: 4
+body: |
+ bb.0:
+ liveins: $q0, $q1
+ ; FP16-LABEL: name: s128_libcall
+ ; FP16: %a:_(s128) = COPY $q0
+ ; FP16: %b:_(s128) = COPY $q1
+ ; FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; FP16: $q0 = COPY %a(s128)
+ ; FP16: $q1 = COPY %b(s128)
+ ; FP16: BL &fminl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
+ ; FP16: %minnum:_(s128) = COPY $q0
+ ; FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; FP16: $q0 = COPY %minnum(s128)
+ ; FP16: RET_ReallyLR implicit $q0
+ ; NO-FP16-LABEL: name: s128_libcall
+ ; NO-FP16: %a:_(s128) = COPY $q0
+ ; NO-FP16: %b:_(s128) = COPY $q1
+ ; NO-FP16: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; NO-FP16: $q0 = COPY %a(s128)
+ ; NO-FP16: $q1 = COPY %b(s128)
+ ; NO-FP16: BL &fminl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
+ ; NO-FP16: %minnum:_(s128) = COPY $q0
+ ; NO-FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; NO-FP16: $q0 = COPY %minnum(s128)
+ ; NO-FP16: RET_ReallyLR implicit $q0
+ %a:_(s128) = COPY $q0
+ %b:_(s128) = COPY $q1
+ %minnum:_(s128) = G_FMINNUM %a, %b
+ $q0 = COPY %minnum(s128)
+ RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index a7952f55e15f..f5a620204fb8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -484,11 +484,12 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_FMINNUM (opcode {{[0-9]+}}): 1 type index
-# DEBUG: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_FMAXNUM (opcode {{[0-9]+}}): 1 type index
-# DEBUG: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. the first uncovered type index: 1, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_FMINNUM_IEEE (opcode {{[0-9]+}}): 1 type index
# DEBUG: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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