[llvm] 3d91d5b - [AArch64][GlobalISel] Mark G_FMINNUM/G_FMAXNUM as floating point opcodes
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 18 13:32:53 PDT 2021
Author: Jessica Paquette
Date: 2021-08-18T13:32:19-07:00
New Revision: 3d91d5b757ff15f1c57a165e5d530320ac1428bd
URL: https://github.com/llvm/llvm-project/commit/3d91d5b757ff15f1c57a165e5d530320ac1428bd
DIFF: https://github.com/llvm/llvm-project/commit/3d91d5b757ff15f1c57a165e5d530320ac1428bd.diff
LOG: [AArch64][GlobalISel] Mark G_FMINNUM/G_FMAXNUM as floating point opcodes
We need to ensure that these end up on FPR to allow imported patterns to
select them.
This will also ensure that we get good regbank selection when dealing with
instructions like G_PHI/G_LOAD/G_STORE which deduce their banks from their
uses/users.
Differential Revision: https://reviews.llvm.org/D108260
Added:
llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
Modified:
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 8c34027f7bb3..aded24580cbe 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -424,6 +424,8 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
case TargetOpcode::G_FRINT:
case TargetOpcode::G_INTRINSIC_TRUNC:
case TargetOpcode::G_INTRINSIC_ROUND:
+ case TargetOpcode::G_FMAXNUM:
+ case TargetOpcode::G_FMINNUM:
return true;
}
return false;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
new file mode 100644
index 000000000000..7a83a527957d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-maxnum.mir
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name: fp_inputs
+legalized: true
+body: |
+ bb.0:
+ liveins: $s0, $s1
+
+ ; CHECK-LABEL: name: fp_inputs
+ ; CHECK: %lhs:fpr(s32) = COPY $s0
+ ; CHECK: %rhs:fpr(s32) = COPY $s1
+ ; CHECK: %maxnum:fpr(s32) = G_FMAXNUM %lhs, %rhs
+ ; CHECK: $s0 = COPY %maxnum(s32)
+ ; CHECK: RET_ReallyLR implicit $s0
+ %lhs:_(s32) = COPY $s0
+ %rhs:_(s32) = COPY $s1
+ %maxnum:_(s32) = G_FMAXNUM %lhs, %rhs
+ $s0 = COPY %maxnum(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: gp_inputs
+legalized: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: gp_inputs
+ ; CHECK: %lhs:gpr(s32) = COPY $w0
+ ; CHECK: %rhs:gpr(s32) = COPY $w1
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %lhs(s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY %rhs(s32)
+ ; CHECK: %maxnum:fpr(s32) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; CHECK: $s0 = COPY %maxnum(s32)
+ ; CHECK: RET_ReallyLR implicit $s0
+ %lhs:_(s32) = COPY $w0
+ %rhs:_(s32) = COPY $w1
+ %maxnum:_(s32) = G_FMAXNUM %lhs, %rhs
+ $s0 = COPY %maxnum(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: gp_use
+legalized: true
+body: |
+ bb.0:
+ liveins: $s0, $s1
+
+ ; CHECK-LABEL: name: gp_use
+ ; CHECK: %lhs:fpr(s32) = COPY $s0
+ ; CHECK: %rhs:fpr(s32) = COPY $s1
+ ; CHECK: %maxnum:fpr(s32) = G_FMAXNUM %lhs, %rhs
+ ; CHECK: $w0 = COPY %maxnum(s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %lhs:_(s32) = COPY $s0
+ %rhs:_(s32) = COPY $s1
+ %maxnum:_(s32) = G_FMAXNUM %lhs, %rhs
+ $w0 = COPY %maxnum(s32)
+ RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
new file mode 100644
index 000000000000..a09043487334
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-minnum.mir
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name: fp_inputs
+legalized: true
+body: |
+ bb.0:
+ liveins: $s0, $s1
+
+ ; CHECK-LABEL: name: fp_inputs
+ ; CHECK: %lhs:fpr(s32) = COPY $s0
+ ; CHECK: %rhs:fpr(s32) = COPY $s1
+ ; CHECK: %minnum:fpr(s32) = G_FMINNUM %lhs, %rhs
+ ; CHECK: $s0 = COPY %minnum(s32)
+ ; CHECK: RET_ReallyLR implicit $s0
+ %lhs:_(s32) = COPY $s0
+ %rhs:_(s32) = COPY $s1
+ %minnum:_(s32) = G_FMINNUM %lhs, %rhs
+ $s0 = COPY %minnum(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: gp_inputs
+legalized: true
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: gp_inputs
+ ; CHECK: %lhs:gpr(s32) = COPY $w0
+ ; CHECK: %rhs:gpr(s32) = COPY $w1
+ ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %lhs(s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY %rhs(s32)
+ ; CHECK: %minnum:fpr(s32) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK: $s0 = COPY %minnum(s32)
+ ; CHECK: RET_ReallyLR implicit $s0
+ %lhs:_(s32) = COPY $w0
+ %rhs:_(s32) = COPY $w1
+ %minnum:_(s32) = G_FMINNUM %lhs, %rhs
+ $s0 = COPY %minnum(s32)
+ RET_ReallyLR implicit $s0
+
+...
+---
+name: gp_use
+legalized: true
+body: |
+ bb.0:
+ liveins: $s0, $s1
+
+ ; CHECK-LABEL: name: gp_use
+ ; CHECK: %lhs:fpr(s32) = COPY $s0
+ ; CHECK: %rhs:fpr(s32) = COPY $s1
+ ; CHECK: %minnum:fpr(s32) = G_FMINNUM %lhs, %rhs
+ ; CHECK: $w0 = COPY %minnum(s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %lhs:_(s32) = COPY $s0
+ %rhs:_(s32) = COPY $s1
+ %minnum:_(s32) = G_FMINNUM %lhs, %rhs
+ $w0 = COPY %minnum(s32)
+ RET_ReallyLR implicit $w0
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