[PATCH] D108201: [AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri accepted this revision.
lebedev.ri added a comment.
This revision is now accepted and ready to land.

We don't actually need *all* the high bits to be zeros,
only the ones that would be potentially shifted-in,
iff we don't truncate them away first.
E.g.: `0b11100111`, target bit width of 4, and shift amount of 0..1: https://alive2.llvm.org/ce/z/jJ85EE

But indeed, we only have the 'min' bitwidth, we can't really model that here,
especially because 'max' bitwidth would differ for different 'min' bitwidths...

So LG, i guess.
@spatel ?



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Comment at: llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp:295
+        MinBitWidth = std::max(MinBitWidth,
+                               SrcBitWidth - KnownLHS.countMinLeadingZeros());
+      }
----------------



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