[PATCH] D108201: [AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev added a comment.

> We don't actually need *all* the high bits to be zeros,
> only the ones that would be potentially shifted-in,

Sure, that's why it's only sufficient condition, not necessary one. Hope it's the most common case in real life.


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https://reviews.llvm.org/D108201