[PATCH] D108201: [AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG

[Anton Afanasyev via Phabricator via llvm-commits]

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Add `lshr` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressions containing
these instructions.

We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are zeros: https://alive2.llvm.org/ce/z/_LytbB

Part of https://reviews.llvm.org/D107766


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108201

Files:
  llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
  llvm/test/Transforms/AggressiveInstCombine/pr50555.ll
  llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
  llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll

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