[PATCH] D108091: [AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp:111
+      if (I->getOpcode() == Instruction::Shl) {
+        KnownBits KnownRHS = computeKnownBits(I->getOperand(1), DL);
+        const unsigned SrcBitWidth = KnownRHS.getBitWidth();
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I think you might want to also pass `DT`, `/*CxtI=*/CurrentTruncInst`;
i guess we don't yet have `AssumptionCache` here in AIC..


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108091/new/

https://reviews.llvm.org/D108091