[PATCH] D108091: [AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev marked 3 inline comments as done.
anton-afanasyev added inline comments.


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Comment at: llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp:111
+      if (I->getOpcode() == Instruction::Shl) {
+        KnownBits KnownRHS = computeKnownBits(I->getOperand(1), DL);
+        const unsigned SrcBitWidth = KnownRHS.getBitWidth();
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lebedev.ri wrote:
> I think you might want to also pass `DT`, `/*CxtI=*/CurrentTruncInst`;
> i guess we don't yet have `AssumptionCache` here in AIC..
No, we haven't `AC`, only `DT`. Do you mean me to add it to AIC to use for `computeKnownBits()`?


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Comment at: llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp:113-115
+        MinBitWidth = KnownRHS.getMaxValue().getZExtValue();
+        if (MinBitWidth != std::numeric_limits<unsigned>::max())
+          MinBitWidth++;
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lebedev.ri wrote:
> 
Thanks, done


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Comment at: llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp:381-383
+      // `shl nsw` is more poisonous if bitwidth is smaller.
+      if (Opc == Instruction::Shl)
+        cast<Instruction>(Res)->setHasNoUnsignedWrap(I->hasNoUnsignedWrap());
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lebedev.ri wrote:
> This doesn't sound right?
> https://alive2.llvm.org/ce/z/DMaieM
> 
> We drop no-wrap flags on all other instructions here, let's just not bother?
Changed, thanks! Also fixed test to tackle this case.


Repository:
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  https://reviews.llvm.org/D108091/new/

https://reviews.llvm.org/D108091