[PATCH] D107400: [RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D107400#2933427 <https://reviews.llvm.org/D107400#2933427>, @luismarques wrote:

> LGTM.
>
>> We can't use the branch opcode encodings directly as that would make the MIR printed values change when new instructions are added.
>
> I'm not sure I understand this point. Can you please elaborate?

I probably shouldn't have used "encodings" there. I meant the enum values assigned by tablegen like RISCV::BEQ RISCV::BNE, etc.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107400/new/

https://reviews.llvm.org/D107400