[PATCH] D107400: [RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 8 15:42:46 PDT 2021
luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.
LGTM.
> We can't use the branch opcode encodings directly as that would make the MIR printed values change when new instructions are added.
I'm not sure I understand this point. Can you please elaborate?
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https://reviews.llvm.org/D107400
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