[PATCH] D107400: [RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Previously we converted ISD condition codes to integers and stored
them directly in our MIR instructions. The ISD enum kind of belongs
to SelectionDAG so that seems like incorrect layering.

This patch instead uses the CondCode node on RISCV::SELECT_CC until
isel and then converts it from ISD encoding to a RISCV specific value.
This value can be converted to/from the RISCV branch opcodes. We
can't use the branch opcode encodings directly as that would make the
MIR printed values change when new instructions are added.

My larger motivation is to possibly implement something like this patch
from gcc https://patchwork.ozlabs.org/project/gcc/patch/20190430234741.8120-1-jimw@sifive.com/#2163277
This will require a new pseudo instruction for select that needs to
carry a branch condition and live probably until RISCVExpandPseudos.
Using an ISD encoding in RISCVExpandPseudos doesn't seem like correct
layering.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107400

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/select-optimize-multiple.mir

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