[PATCH] D107363: [ARM][atomicrmw] Fix CMP_SWAP_32 expand assert

[Tomas Matheson via Phabricator via llvm-commits]

tmatheson updated this revision to Diff 363760.
tmatheson added a comment.

Remove commented lines


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107363/new/

https://reviews.llvm.org/D107363

Files:
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/test/CodeGen/ARM/cmpxchg.mir


Index: llvm/test/CodeGen/ARM/cmpxchg.mir
===================================================================
--- llvm/test/CodeGen/ARM/cmpxchg.mir
+++ llvm/test/CodeGen/ARM/cmpxchg.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
+# RUN: llc -o - %s -mtriple=thumbv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo
 ---
 name: func
 tracksRegLiveness: true
@@ -25,3 +26,11 @@
     ; CHECK: .3:
     dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic (s64))
 ...
+---
+name: func2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $r1, $r2, $r3, $r12, $lr
+    dead early-clobber renamable $r1, dead early-clobber renamable $r2 = CMP_SWAP_32 killed renamable $r3, killed renamable $r12, killed renamable $lr
+...
Index: llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -1647,8 +1647,8 @@
            "CMP_SWAP not expected to be custom expanded for Thumb1");
     assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
            "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
-    assert(ARM::tGPRRegClass.contains(DesiredReg) &&
-           "DesiredReg used for UXT op must be tGPR");
+    assert(UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg) &&
+                             "DesiredReg used for UXT op must be tGPR");
   }
 
   MachineFunction *MF = MBB.getParent();


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D107363.363760.patch
Type: text/x-patch
Size: 1781 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210803/6608dec7/attachment.bin>