[PATCH] D107363: [ARM][atomicrmw] Fix CMP_SWAP_32 expand assert

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp:1650
            "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
-    assert(ARM::tGPRRegClass.contains(DesiredReg) &&
-           "DesiredReg used for UXT op must be tGPR");
+    assert(UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg) &&
+                             "DesiredReg used for UXT op must be tGPR");
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I think it needs brackets around the ||


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Comment at: llvm/test/CodeGen/ARM/cmpxchg.mir:1
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
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This needs to be rerun, to generate the check lines. It is also probably best if both the llc run lines have FileCheck's to check the output, even if they might be different.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107363/new/

https://reviews.llvm.org/D107363