[PATCH] D107363: [ARM][atomicrmw] Fix CMP_SWAP_32 expand assert

[Tomas Matheson via Phabricator via llvm-commits]

tmatheson created this revision.
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This assert is intended to ensure that the high registers are not
selected when it is passed to one of the thumb UXT instructions. However
it was triggering even for 32 bit where no UXT instruction is emitted.

Fixes PR51313.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107363

Files:
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/test/CodeGen/ARM/cmpxchg.mir


Index: llvm/test/CodeGen/ARM/cmpxchg.mir
===================================================================
--- llvm/test/CodeGen/ARM/cmpxchg.mir
+++ llvm/test/CodeGen/ARM/cmpxchg.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
+# RUN: llc -o - %s -mtriple=thumbv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo
 ---
 name: func
 tracksRegLiveness: true
@@ -25,3 +26,13 @@
     ; CHECK: .3:
     dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic (s64))
 ...
+---
+name: func2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; liveins: $r0_r1, $r4_r5, $r3, $r12, $lr
+    ; liveins: $r0, $r1, $r4, $r5, $r3, $lr
+    liveins: $r1, $r2, $r3, $r12, $lr
+    dead early-clobber renamable $r1, dead early-clobber renamable $r2 = CMP_SWAP_32 killed renamable $r3, killed renamable $r12, killed renamable $lr
+...
Index: llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -1647,8 +1647,8 @@
            "CMP_SWAP not expected to be custom expanded for Thumb1");
     assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
            "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
-    assert(ARM::tGPRRegClass.contains(DesiredReg) &&
-           "DesiredReg used for UXT op must be tGPR");
+    assert(UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg) &&
+                             "DesiredReg used for UXT op must be tGPR");
   }
 
   MachineFunction *MF = MBB.getParent();


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