[PATCH] D107160: [AArch64] Do not emit an extra zero-extend for i1 argument
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 30 11:34:11 PDT 2021
efriedma added reviewers: aemerson, paquette.
efriedma added a comment.
On the SelectionDAG ISel side, I'm not really happy we're working around the usual framework for dealing with known bits. Can we use some sort of target-specific equivalent to AssertZExt to encode the known bits, then use those known bits when we generate the call?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D107160/new/
https://reviews.llvm.org/D107160
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