[PATCH] D107160: [AArch64] Do not emit an extra zero-extend for i1 argument

[Eli Friedman via Phabricator via llvm-commits]

efriedma added reviewers: aemerson, paquette.
efriedma added a comment.

On the SelectionDAG ISel side, I'm not really happy we're working around the usual framework for dealing with known bits.  Can we use some sort of target-specific equivalent to AssertZExt to encode the known bits, then use those known bits when we generate the call?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107160/new/

https://reviews.llvm.org/D107160