[PATCH] D107160: [AArch64] Do not emit an extra zero-extend for i1 argument

[Jessica Paquette via Phabricator via llvm-commits]

paquette added a comment.

If it's possible to handle this using AssertZExt on the SDAG side, I think it would be nice to handle it similarly on the GISel side using G_ASSERT_ZEXT.



================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp:1053
+
+  MachineInstr *ArgDef = MRI.getVRegDef(AI.Regs[0]);
+  if (!ArgDef || ArgDef->getOpcode() != TargetOpcode::G_TRUNC)
----------------
I think that you can handle most of the logic in here using MIPatternMatch:

```
Register OrigReg;
if (!mi_match(AI.Regs[0], MRI, m_GTrunc(m_Reg(OrigReg))))
   return false;
```


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp:1062
+  Register OrigReg = Op.getReg();
+  for (const Register &BoolReg : FuncInfo.getBoolRegParms()) {
+    if (BoolReg == OrigReg) {
----------------
Maybe this loop can be replaced with `llvm::any_of`?


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