[PATCH] D106651: [RISCV] Add support for vector saturating add/sub operations

Mon Jul 26 09:00:39 PDT 2021

craig.topper added a comment.

In D106651#2903878 <https://reviews.llvm.org/D106651#2903878>, @frasercrmck wrote:

> In D106651#2900762 <https://reviews.llvm.org/D106651#2900762>, @craig.topper wrote:
>
>> These instructions can set the vxsat bit. How does that interact with other code around that might want to read the vxsat bit?
>
> It's a good question. The `vxsat`  flag can only be read via a CSR, as far as I can tell.
>
> I don't believe we expose access to CSRs via intrinsics. What guarantees do we give to software using inline asm that reads CSRs?
>
> It appears we're modeling the `VXSAT` instruction defs and uses, though we're perhaps not modeling the `VCSR` super register correctly.
>
> On a related note, given these instructions write `VXSAT` we'll probably see some write-after-write scheduling dependencies which I suspect would hamper performance. It's basically a write-only sticky flag so it might be legal to loosen those order dependencies somewhat.

There was a proposal to add intrinsics wrapping inline assembly in https://github.com/riscv/rvv-intrinsic-doc/issues/36 Not sure why a decision hasn't been made on that issue. It looks like the P extension is also proposing to use the vxsat csr.

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https://reviews.llvm.org/D106651