[PATCH] D106651: [RISCV] Add support for vector saturating add/sub operations

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D106651#2900762 <https://reviews.llvm.org/D106651#2900762>, @craig.topper wrote:

> These instructions can set the vxsat bit. How does that interact with other code around that might want to read the vxsat bit?

It's a good question. The `vxsat`  flag can only be read via a CSR, as far as I can tell.

I don't believe we expose access to CSRs via intrinsics. What guarantees do we give to software using inline asm that reads CSRs?

It appears we're modeling the `VXSAT` instruction defs and uses, though we're perhaps not modeling the `VCSR` super register correctly.

On a related note, given these instructions write `VXSAT` we'll probably see some write-after-write scheduling dependencies which I suspect would hamper performance. It's basically a write-only sticky flag so it might be legal to loosen those order dependencies somewhat.


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https://reviews.llvm.org/D106651