[PATCH] D106273: [SVE][AArch64] Improve code generation for vector_splice for Imm > 0

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:245
+  template <signed Min, signed Max, signed Scale>
+  bool SelectEXTImm(SDValue N, SDValue &Imm) {
+    if (!isa<ConstantSDNode>(N))
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Just a thought, but do we even need a `Min` here since it always seems to be `0` anyway? We could just compare directly against `0` in the if statement below.


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Comment at: llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll:206
 
+define <vscale x 2 x half> @splice_nxv2f16_first_idx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
+; CHECK-LABEL: splice_nxv2f16_first_idx:
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Hi @CarolineConcatto it's great that you're adding these unpacked vector test cases! Would it be possible to test a case like this as well?

  %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 2)

The reason I'm interested is because the splice intrinsic maps to the ext instruction only for packed vector types. I'm not entirely sure if the index immediate passed to `ext` will still be correct in this case as it may need scaling.



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  https://reviews.llvm.org/D106273/new/

https://reviews.llvm.org/D106273