[PATCH] D106273: [SVE][AArch64] Improve code generation for vector_splice for Imm > 0

Caroline via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 22 03:40:51 PDT 2021


CarolineConcatto updated this revision to Diff 360755.
CarolineConcatto marked 4 inline comments as done.
CarolineConcatto retitled this revision from "[WIP] Improve code generation for vector_splice for Imm > 0" to "[SVE][AArch64] Improve code generation for vector_splice for Imm > 0".
CarolineConcatto added a comment.
Herald added subscribers: psnobl, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.

- Remove WIP from the title.
- Simplify test in the lowering function.
- Fix indentation in tablegen


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106273/new/

https://reviews.llvm.org/D106273

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

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