[PATCH] D105817: [LV] Enable vectorization of multiple exit loops w/computable exit counts
David Spickett via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 22 07:32:04 PDT 2021
DavidSpickett added a comment.
@reames This commit has broken our 2 stage A64FX SVE bot. (sorry for the late report, took me a while to bisect it)
https://lab.llvm.org/buildbot/#/builders/176/builds/88
This bot builds stage 1 with `-mcpu=a64fx` then uses that to build stage 2 with flags `-mcpu=a64fx -mllvm -aarch64-sve-vector-bits-min=512` and doing so leads to this error from `clang-tblgen`:
[3689/7201] Building AbstractBasicReader.inc...
FAILED: tools/clang/include/clang/AST/AbstractBasicReader.inc
cd /home/tcwg-buildslave/worker/clang-aarch64-sve-vls-2stage/stage2 && /home/tcwg-buildslave/worker/clang-aarch64-sve-vls-2stage/stage2/bin/clang-tblgen -gen-clang-basic-reader -I /home/tcwg-buildslave/worker/clang-aarch64-sve-vls-2stage/llvm/clang/include/clang/AST -I/home/tcwg-buildslave/worker/clang-aarch64-sve-vls-2stage/llvm/clang/include -I/home/tcwg-buildslave/worker/clang-aarch64-sve-vls-2stage/stage2/tools/clang/include -I/home/tcwg-buildslave/worker/clang-aarch64-sve-vls-2stage/stage2/include -I/home/tcwg-buildslave/worker/clang-aarch64-sve-vls-2stage/llvm/llvm/include /home/tcwg-buildslave/worker/clang-aarch64-sve-vls-2stage/llvm/clang/include/clang/AST/PropertiesBase.td --write-if-changed -o tools/clang/include/clang/AST/AbstractBasicReader.inc -d tools/clang/include/clang/AST/AbstractBasicReader.inc.d
/home/tcwg-buildslave/worker/clang-aarch64-sve-vls-2stage/llvm/clang/include/clang/AST/PropertiesBase.td:362:3: error: creation code for Array doesn't refer to property "totalLength"
def : Creator<[{
^
I haven't seen this on any other bot, the code itself seems fine (though first time reading it myself) and if I remove `-mllvm -aarch64-sve-vector-bits-min=512` the build works. So I assume what's happening is something is being vectorised incorrectly, or doing so is uncovering a different issue. It could be particular to SVE.
Obviously "build all of llvm and some of clang" isn't a great reproducer so I'm going to see if I can emit some vectorisation info with the names/locations of the functions that were previously not vectorised and now are.
Any other ideas welcome.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105817/new/
https://reviews.llvm.org/D105817
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