[PATCH] D105817: [LV] Enable vectorization of multiple exit loops w/computable exit counts

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D105817#2896422 <https://reviews.llvm.org/D105817#2896422>, @DavidSpickett wrote:

> Any other ideas welcome.

@DavidSpickett - I took a skim through the SVE code to see if anything obvious fell out, but I didn't spot anything.  Unfortunately, you've got a combination of an architecture I'm unfamiliar with, and an IR feature I'm unfamiliar with.  I don't think I'll be able to help you much without a reproducer and some context.

A couple ideas for you:

1. If you use smaller min bit widths, do you still see the problem?
2. Does setting that flag change the number of loops which get vectorizer?  If not, it must change *how* they get vectorized.
3. Is there a known bug with scalable vectorization and epilogue loops?  This change causes a lot more epilogue loops to be generated.
4. If you change the control knob for preferring fixed vs scalable with SVE registers, does the symptom change?


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