[PATCH] D106497: Add disassembly for the conditioned RSUB immediate instruction for the ARC backend

[Mark Schimmel via Phabricator via llvm-commits]

marksl added inline comments.


================
Comment at: llvm/lib/Target/ARC/ARCInstrInfo.td:164
+  let Defs = [STATUS32], Constraints = "$A = $B" in {
+    def _cc_rru6 : F32_DOP_CC_RRU6<major, mincode, 0, (outs GPR32:$A),
+                                   (ins immU6:$U6, ccond:$cc, GPR32:$B),
----------------
This form Refs=[STATUS32]


================
Comment at: llvm/lib/Target/ARC/ARCInstrInfo.td:169
+
+    def _cc_f_rru6 : F32_DOP_CC_RRU6<major, mincode, 1, (outs GPR32:$A),
+                                     (ins immU6:$U6, ccond:$cc, GPR32:$B),
----------------
This form Defs=[STATUS32] and Refs=[STATUS32]


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106497/new/

https://reviews.llvm.org/D106497