[PATCH] D106497: Add disassembly for the conditioned RSUB immediate instruction for the ARC backend

[Thomas Johnson via Phabricator via llvm-commits]

thomasjohns created this revision.
thomasjohns added reviewers: marksl, gyiu.
Herald added a subscriber: hiraditya.
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This adds an entry for a conditioned RSUB with a register-register-u6 pattern (e.g. `rsub.ne %r0, %r0, 31`) in `ARCInstrInfo.td` and `ARCInstrFormats.td` and demonstrates the ability to decode this instruction from an object file.

For example, when disassembling the object file derived from compiling:

  int f(int x) {
    return __builtin_clz(x);
  }

we used to have:

  00000000 <f>:
         0: 2f 28 13 80   <unknown>
         4: ca 20 21 08   mov.eq  %r0, 32
         8: e0 7f         j_s.d   [%blink]
         a: ce 20 e2 07   <unknown>

but now we have:

  00000000 <f>:
         0: 2f 28 13 80   <unknown>
         4: ca 20 21 08   mov.eq  %r0, 32
         8: e0 7f         j_s.d   [%blink]
         a: ce 20 e2 07   rsub.ne %r0, %r0, 31

This also adds two test cases for the disassembly of `MOVcc_ru6` which where accidently dropped from a previous revision: https://reviews.llvm.org/D105560.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106497

Files:
  llvm/lib/Target/ARC/ARCInstrFormats.td
  llvm/lib/Target/ARC/ARCInstrInfo.td
  llvm/test/MC/Disassembler/ARC/alu.txt
  llvm/test/MC/Disassembler/ARC/misc.txt

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