[PATCH] D106497: Add disassembly for the conditioned RSUB immediate instruction for the ARC backend

[Thomas Johnson via Phabricator via llvm-commits]

thomasjohns added inline comments.


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Comment at: llvm/lib/Target/ARC/ARCInstrInfo.td:169
+
+    def _cc_f_rru6 : F32_DOP_CC_RRU6<major, mincode, 1, (outs GPR32:$A),
+                                     (ins immU6:$U6, ccond:$cc, GPR32:$B),
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marksl wrote:
> This form Defs=[STATUS32] and Refs=[STATUS32]
Hi Mark, I'm not sure what `Refs` is referring to. Is there something that should be changed here?


Repository:
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  https://reviews.llvm.org/D106497/new/

https://reviews.llvm.org/D106497