[PATCH] D106265: [AArch64][SVE] Zero-overhead transfer between Neon and SVE registers

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm planned changes to this revision.
peterwaller-arm added a comment.

BRB later today with fixes. Early comments welcomed on the approach.



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Comment at: llvm/test/CodeGen/AArch64/dag-combine-insert-elt.ll:13
+  %b = insertelement <vscale x 2 x double> undef, double 0.0, i32 0
+  %a = insertelement <vscale x 2 x double> undef, double 1.0, i32 1
+  ret <vscale x 2 x double> %a
----------------
Accidental double-insert-into-undef here.


================
Comment at: llvm/test/CodeGen/AArch64/dag-combine-insert-elt.ll:26
+  %b = insertelement <vscale x 2 x double> undef, double %e0, i32 0
+  %a = insertelement <vscale x 2 x double> undef, double %e1, i32 1
+  ret <vscale x 2 x double> %a
----------------
And here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106265/new/

https://reviews.llvm.org/D106265