[PATCH] D106265: [AArch64][SVE] Zero-overhead transfer between Neon and SVE registers

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm created this revision.
peterwaller-arm added reviewers: paulwalker-arm, efriedma, bsmith, DavidTruby, sdesmalen, Matt, david-arm.
Herald added subscribers: ecnelises, steven.zhang, psnobl, hiraditya, kristof.beyls, tschuett.
peterwaller-arm requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

A pattern for moving data from a Neon ACLE type into an SVE ACLE type
involves extracting the two double-lanes of the Neon register and
inserting them into an SVE register using two DUPs with VL1 and VL2.

This must compile to a NOP.

To achieve this, this patch adds support in DAGCombine to support the
INSERT_VECTOR_ELT => BUILD_VECTOR combine. Since BUILD_VECTOR does not
support scalable vectors, the insertions are pushed into a fixed
BUILD_VECTOR through an INSERT_SUBVECTOR to make it scalable again.

With this DAGCombine in place, existing BUILD_VECTOR combines are able
neatly optimize away bitcast/extractelement/shuffle etc.

Since not all Scalable vector types are supported for INSERT_SUBVECTOR,
I introduce a TargetLoweringInfo::isInsertSubvectorLegal to query
whether to perform the combine.

Two dup => insertelement patterns are added in instCombineSVEDup:

  (dup vec VL1 elem0)
  => (insertelement vec elem0 0)
  
  (dup (dup vec VL2 elem1) VL1 elem0)
  => (insertelement (insertelement vec elem1 1) elem0 0)

... which enable the BUILD_VECTOR optimization to work.

Reference:

  "Move data between Advanced SIMD (Neon) and SVE ACLE types"
  https://developer.arm.com/documentation/ka004612/latest
  KA004612


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106265

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/CodeGen/AArch64/dag-combine-insert-elt.ll
  llvm/test/CodeGen/AArch64/sve-insert-element.ll
  llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
  llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-dup.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D106265.359751.patch
Type: text/x-patch
Size: 18408 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210719/6f130811/attachment.bin>