[PATCH] D106079: [AMDGPU] Divergence-driven compare operations instruction selection

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:594
+          if (SrcReg == AMDGPU::SCC) {
+            Register SCCCopy = MRI->createVirtualRegister(ST.isWave32() ?
+               &AMDGPU::SReg_32RegClass : &AMDGPU::SReg_64_XEXECRegClass);
----------------
TRI->getBoolRC()?


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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:598
+                        std::next(MachineBasicBlock::iterator(MI)),
+                        MI.getDebugLoc(), TII->get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64), SCCCopy)
+                    .addImm(-1)
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It is certainly too wide, you need to use clang-format.


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Comment at: llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll:5135
+; GFX9-NEXT:    s_cmp_lg_u64 s[0:1], 0
+; GFX9-NEXT:    s_cselect_b64 vcc, -1, 0
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
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This looks like a regression. A common one.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106079/new/

https://reviews.llvm.org/D106079