[PATCH] D106079: [AMDGPU] Divergence-driven compare operations instruction selection

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 15 12:26:29 PDT 2021


arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:592
+        if (MI.isCopy()) {
+          Register SrcReg = MI.getOperand(1).getReg();
+          if (SrcReg == AMDGPU::SCC) {
----------------
When do copies from SCC appear? I thought the InstrEmitter could essentially always avoid these


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106079/new/

https://reviews.llvm.org/D106079



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