[PATCH] D106079: [AMDGPU] Divergence-driven compare operations instruction selection

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:592
+        if (MI.isCopy()) {
+          Register SrcReg = MI.getOperand(1).getReg();
+          if (SrcReg == AMDGPU::SCC) {
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When do copies from SCC appear? I thought the InstrEmitter could essentially always avoid these


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  https://reviews.llvm.org/D106079/new/

https://reviews.llvm.org/D106079