[PATCH] D106079: [AMDGPU] Divergence-driven compare operations instruction selection

[Alexander via Phabricator via llvm-commits]

alex-t created this revision.
alex-t added a reviewer: rampitec.
Herald added subscribers: foad, kerbowa, asbirlea, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm, MatzeB.
alex-t requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

Description: This change enables the compare operations to be selected to SALU/VALU form

  dependent of the SDNode divergence flag.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106079

Files:
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/test/CodeGen/AMDGPU/addrspacecast.ll
  llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/branch-relaxation.ll
  llvm/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll
  llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
  llvm/test/CodeGen/AMDGPU/ctlz.ll
  llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
  llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll
  llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
  llvm/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll
  llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
  llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll
  llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
  llvm/test/CodeGen/AMDGPU/icmp64.ll
  llvm/test/CodeGen/AMDGPU/idiv-licm.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll
  llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
  llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
  llvm/test/CodeGen/AMDGPU/load-select-ptr.ll
  llvm/test/CodeGen/AMDGPU/min.ll
  llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
  llvm/test/CodeGen/AMDGPU/optimize-negated-cond.ll
  llvm/test/CodeGen/AMDGPU/or.ll
  llvm/test/CodeGen/AMDGPU/sad.ll
  llvm/test/CodeGen/AMDGPU/saddo.ll
  llvm/test/CodeGen/AMDGPU/sdiv.ll
  llvm/test/CodeGen/AMDGPU/sdiv64.ll
  llvm/test/CodeGen/AMDGPU/select-constant-cttz.ll
  llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
  llvm/test/CodeGen/AMDGPU/select-opt.ll
  llvm/test/CodeGen/AMDGPU/select-vectors.ll
  llvm/test/CodeGen/AMDGPU/selectcc-opt.ll
  llvm/test/CodeGen/AMDGPU/selectcc.ll
  llvm/test/CodeGen/AMDGPU/setcc-opt.ll
  llvm/test/CodeGen/AMDGPU/setcc.ll
  llvm/test/CodeGen/AMDGPU/setcc64.ll
  llvm/test/CodeGen/AMDGPU/shift-i128.ll
  llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
  llvm/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll
  llvm/test/CodeGen/AMDGPU/sign_extend.ll
  llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
  llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
  llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
  llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
  llvm/test/CodeGen/AMDGPU/srem64.ll
  llvm/test/CodeGen/AMDGPU/udiv64.ll
  llvm/test/CodeGen/AMDGPU/udivrem.ll
  llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
  llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
  llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
  llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
  llvm/test/CodeGen/AMDGPU/urem64.ll
  llvm/test/CodeGen/AMDGPU/v_cndmask.ll
  llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
  llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
  llvm/test/CodeGen/AMDGPU/vselect.ll
  llvm/test/CodeGen/AMDGPU/wave32.ll
  llvm/test/CodeGen/AMDGPU/zero_extend.ll

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