[PATCH] D105572: [AArch64][SME] Add load and store instructions

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, david-arm, dmgreen, ostannard, CarolineConcatto, kmclaughlin.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
c-rhodes requested review of this revision.
Herald added a project: LLVM.

This patch adds support for following contiguous load and store
instructions:

- LD1B, LD1H, LD1W, LD1D, LD1Q
- ST1B, ST1H, ST1W, ST1D, ST1Q

A new register class and operand is added for the 32-bit vector select
register W12 <https://reviews.llvm.org/W12>-W15. The differences in the following tests which have been
re-generated are caused by the introduction of this register class:

- llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
- llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
- llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
- llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

D88663 <https://reviews.llvm.org/D88663> attempts to resolve the issue with the store pair test
differences in the AArch64 load/store optimizer.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105572

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
  llvm/lib/Target/AArch64/SMEInstrFormats.td
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
  llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1b.s
  llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1d.s
  llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1h.s
  llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1q.s
  llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1w.s
  llvm/test/MC/AArch64/SME/st1b-diagnostics.s
  llvm/test/MC/AArch64/SME/st1b.s
  llvm/test/MC/AArch64/SME/st1d-diagnostics.s
  llvm/test/MC/AArch64/SME/st1d.s
  llvm/test/MC/AArch64/SME/st1h-diagnostics.s
  llvm/test/MC/AArch64/SME/st1h.s
  llvm/test/MC/AArch64/SME/st1q-diagnostics.s
  llvm/test/MC/AArch64/SME/st1q.s
  llvm/test/MC/AArch64/SME/st1w-diagnostics.s
  llvm/test/MC/AArch64/SME/st1w.s
  llvm/test/MC/AArch64/neon-diagnostics.s

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