[PATCH] D103955: [MCA] Use LSU for the in-order pipeline

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added inline comments.


================
Comment at: llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-noalias.s:95-96
+
+# CHECK:      [0,0]     DeeeE.    ..   str	x1, [x10]
+# CHECK-NEXT: [0,1]     .DeeeE    ..   str	x1, [x10]
+# CHECK-NEXT: [0,2]     .DeeE.    ..   ldr	x2, [x10]
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dmgreen wrote:
> I think I would expect most CPU's to work like this, whether the addresses alias or not :)
You mean the store sequence. Of course.

My concern was related to instructions that appear to commit out of order like the load and the nop after it.
We have flag RetireOOO for cases where we want to allow it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D103955/new/

https://reviews.llvm.org/D103955