[PATCH] D100167: [AIX] Adjust CSR order to avoid breaking ABI regarding traceback
Kai Luo via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 30 00:36:43 PDT 2021
lkail added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCSubtarget.h:421
+ return 2;
+ return 0;
+ }
----------------
shchenz wrote:
> Can we use 0 here? 0 is not a valid allocation order index in the td file?
`0` corresponds to the default allocation order which is defined as the last argument of `RegisterClass`.
This can be checked in `PPCGenRegisterInfo.inc`
```
static inline unsigned GPRCAltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
}
static ArrayRef<MCPhysReg> GPRCGetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R0, PPC::R1, PPC::FP, PPC::BP };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];
const ArrayRef<MCPhysReg> Order[] = {
makeArrayRef(MCR.begin(), MCR.getNumRegs()),
makeArrayRef(AltOrder1),
makeArrayRef(AltOrder2)
};
const unsigned Select = GPRCAltOrderSelect(MF);
assert(Select < 3);
return Order[Select];
}
```
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D100167/new/
https://reviews.llvm.org/D100167
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