[PATCH] D105110: [AArch64] Fix for custom lowering <4 x i8> loads

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4507
 
-  SDValue Load = DAG.getLoad(MVT::f32, DL, DAG.getEntryNode(),
+  SDValue Load = DAG.getLoad(MVT::f32, DL, Op.getOperand(0),
                              LoadNode->getBasePtr(), MachinePointerInfo());
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Minor change for code clarity.


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  https://reviews.llvm.org/D105110/new/

https://reviews.llvm.org/D105110