[PATCH] D105016: [TargetLowering][AArch64][SVE] Take into account accessed type when clamping address

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7796
     if (auto *IdxCst = dyn_cast<ConstantSDNode>(Idx))
-      if (IdxCst->getZExtValue() < NElts)
+      if (IdxCst->getZExtValue() + NumSubElts <= NElts)
         return Idx;
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Question: Shouldn't this remain `<`? My thinking: Logically, the thing on the left is the maximum index, and when you increment that thing, it needs to remain less than NElts to still be a valid index.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7819
+  return getVectorSubVecPointer(DAG, VecPtr, VecVT,
+                                VecVT.getVectorElementType(), Index);
+}
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Did you entertain constructing a 1-element vector here and getting rid of the special case?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105016/new/

https://reviews.llvm.org/D105016