[PATCH] D104782: [AArch64] Custom lower <4 x i8> loads

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Missing testcases for load+ext to `<4 x i16>`.



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Comment at: llvm/test/CodeGen/AArch64/neon-extload.ll:38
+; BE-NEXT:    ldr s0, [x0]
+; BE-NEXT:    rev32 v0.8b, v0.8b
+; BE-NEXT:    ushll v0.8h, v0.8b, #0
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SjoerdMeijer wrote:
> I am trying to remember how big-endian works in LLVM, but since I noticed these reverse here, this looked okay'ish to me, but I haven't tested BE. Any opinions on this welcome (while I look a bit more at this)....
Looks fine to me.  The rev32 comes out of lowering the ISD::BITCAST.


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  https://reviews.llvm.org/D104782/new/

https://reviews.llvm.org/D104782