[PATCH] D104782: [AArch64] Custom lower <4 x i8> loads

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1129
+
+    setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Custom);
+    setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Custom);
----------------
What about v4i16 as well? And EXTLOAD (which is probably fine to treat as a ZEXTLOAD).


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4481
+                                         SelectionDAG &DAG) const {
+  SDLoc Dl(Op);
+  LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
----------------
It may be worth checking or asserting that the type is v4i32/v4i16.

Also DL is more common.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4502
+  SDValue BC = DAG.getNode(ISD::BITCAST, Dl, MVT::v8i8, Vec);
+  SDValue Ext = DAG.getNode(ExtType, Dl, MVT::v8i16, BC,
+                            DAG.getValueType(MVT::v8i8));
----------------
SIGN_EXTEND/ZERO_EXTEND do not need a second VT argument, I don't believe.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4506
+                  DAG.getConstant(0, Dl, MVT::i64));
+  Ext = DAG.getNode(ISD::SIGN_EXTEND, Dl, MVT::v4i32, Ext,
+                            DAG.getValueType(MVT::v4i16));
----------------
ISD::SIGN_EXTEND > ExtType?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104782/new/

https://reviews.llvm.org/D104782