[PATCH] D104782: [AArch64] Custom lower <4 x i8> loads

Thu Jun 24 01:00:26 PDT 2021

SjoerdMeijer added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1129
+
+    setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Custom);
+    setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Custom);
----------------
dmgreen wrote:
> What about v4i16 as well? And EXTLOAD (which is probably fine to treat as a ZEXTLOAD).
I thought the v4i16 were already handled, but will double check and precommit some tests for this (the new test in this patch, extended with v4i16 cases ) if we don't have them already.

Yeah, I thought about EXTLOAD, but wasn't sure how to trigger this, but will look into this.

================
Comment at: llvm/test/CodeGen/AArch64/neon-extload.ll:38
+; BE-NEXT:    ldr s0, [x0]
+; BE-NEXT:    rev32 v0.8b, v0.8b
+; BE-NEXT:    ushll v0.8h, v0.8b, #0
----------------
efriedma wrote:
> SjoerdMeijer wrote:
> > I am trying to remember how big-endian works in LLVM, but since I noticed these reverse here, this looked okay'ish to me, but I haven't tested BE. Any opinions on this welcome (while I look a bit more at this)....
> Looks fine to me.  The rev32 comes out of lowering the ISD::BITCAST.
Thanks for confirming!

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104782/new/

https://reviews.llvm.org/D104782