[PATCH] D104205: [X86] Schedule-model second (mask) output of GATHER instruction

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM with one (optional) rename minor - cheers



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Comment at: llvm/lib/Target/X86/X86Schedule.td:128
 def WriteMove    : SchedWrite;
+def WriteGatherMaskWriteback : SchedWrite;
 def WriteCopy    : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
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RKSimon wrote:
> Maybe call this WriteVecMaskedGather to more closely match the other vector load/store classes? Maybe move it to be with the WriteVecMaskedLoad defs as well for clarity.
> 
> I'm assuming we don't need separate float/integer classes for this?
OK, very pedantic but maybe call this WriteVecMaskedGatherWriteback so that it matches the naming convention for vector loads and will match if we add masked gather classes in the future (although tbh they are so diverse in characteristic that it might be easier to just use customs).


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