[PATCH] D104205: [X86] Schedule-model second (mask) output of GATHER instruction

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


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Comment at: llvm/lib/Target/X86/X86SchedBroadwell.td:210
+// Model the effect of clobbering the read-write mask operand of the GATHER operation.
+// Does not cost anything by itself, only has latency, matching that of the WriteLoad,
+defm : X86WriteRes<WriteGatherMaskWriteback, [], 5, [], 0>;
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RKSimon wrote:
> Why does it match a scalar load latency and not a vector load latency?
As you can see in `llvm/lib/Target/X86/X86InstrAVX512.td`/`llvm/lib/Target/X86/X86InstrSSE.td` changes,
for gather, `WriteLoad` is used for some reason. This simply mimics that.
I do guess it should be `WriteVecLoadX`/`WriteVecLoadY`, but that seems like a separate change?


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  https://reviews.llvm.org/D104205/new/

https://reviews.llvm.org/D104205