[PATCH] D101469: [RISCV] Enable interleaved vectorization for RVV

[Luke via Phabricator via llvm-commits]

luke957 added a comment.

In D101469#2801767 <https://reviews.llvm.org/D101469#2801767>, @craig.topper wrote:

> I just noticed that this enabled interleaving in the loop vectorizer even when the V extension isn't enabled. So we now generate interleaved scalar code in some cases. Was that intentional?

Thanks for reminding me. Sorry for my carelessness.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101469/new/

https://reviews.llvm.org/D101469