[PATCH] D101469: [RISCV] Enable interleaved vectorization for RVV

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I just noticed that this enabled interleaving in the loop vectorizer even when the V extension isn't enabled. So we now generate interleaved scalar code in some cases. Was that intentional?


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D101469/new/

https://reviews.llvm.org/D101469